1. Field of the Invention
The present invention relates to synchronous frequency dividing circuits and more particularly to a synchronous frequency dividing circuit for outputting frequency-divided signals in synchronization with a clock signal.
2. Description of the Background Art
The circuitry formed of connected multiple stages of delay type flip-flop circuits DFF01-DFF03 of which outputs are fed back to the inputs as shown in FIG. 23 is a typical frequency dividing circuit. Since flip-flop circuits DFF01-DFF03 each cause delay, signals f/2, f/4, f/8 which are divided by the circuits are delayed from a rise of a clock signal f by delays d1-d3 as shown in FIG. 24. Since divided signals f/2, f/4, f/8 drive different loads, delays d1-d3 are different from one another. Further, delays d1-d3 are varied according to an operating frequency and the logical state of a load. When a logic circuit is formed by utilizing clock signal f and divided signals f/2, f/4, f/8, a circuit for adjusting delays d1-d3 becomes complicated.
As a result, the number of transistors increases, which also increases power consumption.
In order to solve such problems, Japanese Patent Laying-Open No. 5-136691 discloses the frequency dividing circuit for latching divided signals f/2, f/4, f/8 by flip-flops DFF011-DFF013 and outputting divided signals f/2, f14, f/8 in synchronization with clock signal f as shown in FIG. 25.
In the frequency dividing circuit as shown in FIG. 25, however, divided signals f/2, f/4, f/8 are synchronized with clock signal f, exactly with a delay of time d4, as shown in FIG. 26. Further, divided signals f/2, f/4, f/8 are not in phase with one another.